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* this document contains certa in information on a new product. specifications and information herein are subject to change wit hout notice. document number: mc33gd3000 rev. 6.0, 8/2018 nxp semiconductors advance information ? nxp b.v. 2018. three phase field effect transistor pre-driver the 33gd3000 is a field effect t ransistor (fet) pre-driver desi gned for three phase motor control and similar applications. i t meets the stri ngent requirements of autom otive applications and is fully aec-q100 g rade 1 qualified. the ic contains three high-side fet pre-drivers and three low-s ide fet pre- drivers. three external bootstra p capacitors prov ide gate charg e to the high- side fets. the ic interfaces to a mcu via si x direct input control signals , an spi port for device setup and asynchronous reset, enable and interrupt signa ls. both 5.0 v and 3.0 v logic level inputs are accepted and 5.0 v logic level outputs are provided. the integrated circuit (ic) uses smartmos technology. features ? fully specified from 8.0 v to 40 v covers 12 v and 24 v automotive systems ? extended operating range from 6.0 v to 60 v covers 12 v and 48 v systems ? gate drive capabili ty of 1.0 a to 2.5 a ? protection against reverse charge injection from cgd and cgs o f external fets ? includes a charge pump to suppor t full fet drive at low batter y voltages ? dead time is programma ble via the spi port ? simultaneous output capability enabled via safe spi command ? aec-q100 grade 1 qualified figure 1. 33gd3000 simplif ied application diagram three phase pre-driver ep suffix (pb-free) 98asa00654d 56-pin qfn applications automotive systems ? electro-hydraulic and electric power steering ? braking pump ? engine and transmission control ? belt starter generator ? turbo pump ? actuator control ? motor control 33gd3000 vpump pump vsup vpwr vls vdd px_hs px_ls phasex cs si sclk so rst int pa_hs_g pb_hs_g pc_hs_g pa_hs_s pb_hs_s pc_hs_s pa_ls_g pb_ls_g pc_ls_g px_ls_s amp_p amp_n amp_out gnd 33gd3000 v sys mcu or dsp 3 3 3 r sen en1 vss en2
analog integrated circuit device data 2 nxp semiconductors 33gd3000 1 orderable parts table 1. orderable pa rt variations part number temperature (t a ) package MC33GD3000EP (1) -40 c to 125 c 56-pin qfn notes 1. to order parts in tape and reel, add the r2 suffix to the par t number.
analog integrated circuit device data nxp semiconductors 3 33gd3000 2 internal block diagram figure 2. 33gd3000 simplif ied internal block diagram vpump pump vsup vpwr vls vdd px_hs px_ls phasex cs si sclk so rst int amp_p amp_n amp_out px_ls_s main charge pump pgnd en1 en2 oc_out gnd(2) px_boot px_hs_g px_hs_s px_ls_g oc_th vls_cap trickle charge pump hold -off circuit oscillator control logic 5.0 v reg. vdd vls reg. uv detect t-lim + - + - + - 1.4 v + - vsup vsup + - overcurrent comp. i-sense amp. high- side driver low- side driver 3 3 3 3x desat. comp phase comp. vss
analog integrated circuit device data 4 nxp semiconductors 33gd3000 3 pin connections 3.1 pinout diagram figure 3. 33gd300 0 pin connections a functional description of each pin can be found in the functional pin description section beginning on page 21 . table 2. 33gd3000 pin definitions pin pin name pin function formal name definition 1 pa_boot analog input phase a bootstrap bootstrap capacitor for phase a 2, 3, 5, 7, 13, 17, 41, 42 nc no connect no connection 4 vls analog output vls regulator vls regulator output; power supply for the gate drives 6 vpwr power input voltage power power supply input for gate drives 8 phasea digital output phase a totem pole output of phase a comparator; this output is low whe n the voltage on pa_hs_s (source of high-side fet) is less than 50% o f v sup 9 pgnd ground power ground power ground for charge pump pa_boot nc nc vls nc vpwr nc phasea pgnd en1 en2 rst_b nc pump vpump vsup nc phaseb phasec pa_hs_b pa_ls vdd pb_hs_b pb_ls int cs_b si pa_ls_g pa_ls_s pb_boot pb_hs_g pb_ls_s pb_ls_g pb_hs_s pc_boot pc_hs_s pc_hs_g pc_ls_s nc nc vls_cap gnd gnd vss oc_th oc_out amp_p amp_n amp_out pc_hs_b pc_ls so sclk transparent top view pa_hs_g pa_hs_s 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 ep pc_ls_g
analog integrated circuit device data nxp semiconductors 5 33gd3000 10 en1 digital input enable 1 logic signal input must be high (a nded with en2) to enable any gate drive output. 11 en2 digital input enable 2 logic signal input must be high (a nded with en1) to enable any gate drive output 12 rst_b digital input reset reset input 14 pump power drive out pump charge pump output 15 vpump power input voltage pump charge pump supply 16 vsup analog input supply voltage supply voltage to the load. thi s pin is to be connected to the common drains of the external high-side fets 18 phaseb digital output phase b totem pole output of phase b comparator. this output is low whe n the voltage on pb_hs_s (source of high-side fet) is less than 50% o f v sup 19 phasec digital output phase c totem pole output of phase c comparator. this output is low whe n the voltage on pc_hs_s (source of high-side fet) is less than 50% o f v sup 20 pa_hs_b digital input phase a high-side active low input logic signal e nables the high-side driver for phase a 21 pa_ls digital input phase a low-side active high input logic signal e nables the low-side driver for phase a 22 vdd analog output vdd regulator vdd regulator output capacitor connection 23 pb_hs_b digital input phase b high-side active low input logic signal e nables the high-side driver for phase b 24 pb_ls digital input phase b low-side active high input logic signal e nables the low-side driver for phase b 25 int digital output interrupt interrupt pin output 26 cs_b digital input chip select chip select input. it frames sp i commands and enables spi port. 27 si digital input serial in input data for spi port. clocked on the falling edge of sclk, m sb first 28 sclk digital input serial clock clock for spi port and typically is 3.0 mhz 29 so digital output serial out output data for spi port. tri-state until cs becomes low. 30 pc_ls digital input phase c low-side active high input logic signal e nables the low-side driver for phase c 31 pc_hs_b digital input phase c high-side active low input logic signal e nables the high-side driver for phase c 32 amp_out analog output amplifier output output of the current-sensing amplifier 33 amp_n analog input amplifier invert inverting input of the current-sensing amplifier 34 amp_p analog input amplifier non-invert non-inverting input of the current-sensing amplifier 35 oc_out digital output overcurrent out totem pole digital output of the overcurrent comparator 36 oc_th analog input overcurrent threshold threshold of the overcurrent detector 37 vss ground voltage source supply ground reference for logic interface and power supplies 38, 39 gnd ground ground substrate and esd ref erence, connect to vss 40 vls_cap analog output vls regulator output capacitor vls regulator connection for add itional output capacitor, provi ding low impedance supply source for low-side gate drive 43 pc_ls_s power input phase c low-side source source connection for phase c low-side fet 44 pc_ls_g power output phase c low-side gate drive gate drive output for phase c low-side table 2. 33gd3000 pin definitions pin pin name pin function formal name definition
analog integrated circuit device data 6 nxp semiconductors 33gd3000 45 pc_hs_s power input phase c high-side source source connection for phase c high-side fet 46 pc_hs_g power output phase c high-side gate drive gate drive for output phase c high-side fet 47 pc_boot analog input phase c bootstrap bootstrap capacitor for phase c 48 pb_ls_s power input phase b low-side source source connection for phase b low-side fet 49 pb_ls_g power output phase b low-side gate drive gate drive for output phase b low-side 50 pb_hs_s power input phase b high-side source source connection for phase b high-side fet 51 pb_hs_g power output phase b high-side gate drive gate drive for output phase b high-side 52 pb_boot analog input phase b bootstrap bootstrap capacitor for phase b 53 pa_ls_s power input phase a low-side source source connection for phase a low-side fet 54 pa_ls_g power output phase a low-side gate drive gate drive for output phase a low-side 55 pa_hs_s power input phase a high-side source source connection for phase a high-side fet 56 pa_hs_g power output phase a high-side gate drive gate drive for output phase a high-side ep ground exposed pad device performs as specified with the exposed pad un-terminated (floating) however, it is recommended the exposed pad be termin ated to pin 29 (vss) and system ground table 2. 33gd3000 pin definitions pin pin name pin function formal name definition
analog integrated circuit device data nxp semiconductors 7 33gd3000 4 electrical characteristics 4.1 maximum ratings table 3. maximum ratings all voltages are with respect to v ss unless otherwise noted. exceeding these ratings may cause a ma lfunction or permanent damage to the device. symbol ratings value unit notes electrical ratings v sup vsup supply voltage ? normal operation (steady-state) ? transient survival (2) 60 -1.5 to 80 v (2) v pwr vpwr supply voltage ? normal operation (steady-state) ? transient survival 58 -1.5 to 80 v (2) v pump charge pump (pump, vpump) -0.3 to 40 v v ls vls regulator outputs (vls , vls_cap) -0.3 to 18 v v dd logic supply voltage -0.3 to 7.0 v v out logic output (int, so, phasea, phaseb, phasec, oc_out) -0.3 to 7 .0 v (3) v in logic input pin voltage (en1, en2, px_hs , px_ls, si, sclk, cs , rst ) 10 ma -0.3 to 7.0 v v in_a amplifier input voltage ? (both inputs-gnd), (amp_p - g nd) or (amp_n - gnd) 6.0 ma sour ce or sink -7.0 to 7.0 v v oc overcurrent comparator threshold 10 ma -0.3 to 7.0 v v boot v hs_g v ls_g driver output voltage ? high-side bootstrap (pa_boot, pb_boot, pc_boot) ? high-side (pa_hs_g, pb_hs_g, pc_hs_g) ? low-side (pa_ls_g , pb_ls_g, pc_ls_g) 75 75 16 v (4) v hs_g v hs_s v ls_g v ls_s driver voltage transient survival ? high-side (pa_hs_g, pb_hs_g , pc_hs_g, pa_hs_s, pb_hs_s, pc_hs_s) ? low-side (pa_ls_g, pb_ls_g, pc _ls_g, pa_ls_s, pb_ls_s, pc_ls_ s) -7.0 to 75.0 -7.0 to 75.0 -7.0 to 18.0 -7.0 to 7.0 v (5) v esd esd voltage ? human body model - hbm (all pi ns except for the pins listed b elow) pins: pa_boot, pa_hs_s, pa_hs_g , pb_boot, pb_hs_s, pb_hs_g, pc_boot, pc_hs_s, pc_hs_g, vpwr ? charge device model - cdm ? corner pins ? all other pins 2000 1000 300 250 v (6) notes 2. the device can withstand load dump transient as defined by is o 7637 with peak voltage of 80 v. 3. short-circuit proof, the dev ice is not damaged or induce unex pected behavior due to shorts to external sources within this r ange. 4. this voltage should not be ap plied without taking voltage at hs_s and voltage at px_ls_s into account. 5. actual operational limitations m ay differ from survivability limits. the v ls - v ls_s differential and the v boot - v hs_s differential must be greater than 3.0 v to ensure the output gate drive maintains a commande d off condition on the output. 6. esd testing is performed in accordance with the human body mo del (hbm) (c zap = 100 pf, r zap = 1500 ) and the charge device model (cdm), robotic (c zap = 4.0 pf).
analog integrated circuit device data 8 nxp semiconductors 33gd3000 thermal ratings t stg storage temperature -55 to +150 c t j operating junction temperature -40 to +150 c r jc thermal resistance ? junction-to-case 1.5 c/w (7) t solder soldering temperature note 9 c (8) notes 7. case is considered ep - pin 55 under the body of the device. the actual power dissipation of the device is dependent on the operating mode, the heat transfer characteristics o f the board and layout and the o perating voltage. see figure 23 and figure 24 for examples of power dissipation profiles of two common configurations. operation above the maxi mum operating junction temperature results in a reduction in re liability leading to malfunction or permanent damage to the device. 8. pin soldering temperature li mit is for 10 seconds maximum dur ation. not designed for immersi on soldering. exceeding these li mits may cause malfunction or permanent damage to the device. 9. nxps package reflow capability meets pb-free requirements fo r jedec standard j-std-020c. for peak package reflow temperatur e and moisture sensitivity levels (msl) , go to www.nxp.com, search by part number (remove prefixes/suffixes and enter the core id) t o view all orderable parts, and review parametrics. table 3. maximum ra tings (continued) all voltages are with respect to v ss unless otherwise noted. exceeding these ratings may cause a ma lfunction or permanent damage to the device. symbol ratings value unit notes
analog integrated circuit device data nxp semiconductors 9 33gd3000 4.2 static electrical characteristics table 4. static electrical characteristics characteristics noted under conditions 8.0 v v pwr = v sup 40 v , - 40 c t a 125 c, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditi ons, unless otherwise noted. symbol characteristic min. typ. max. unit notes power inputs v pwr_st vpwr supply voltage startup threshold C 6.0 8.0 v (10) i sup vsup supply current, v pwr = v sup = 40 v rst and enable = 5.0 v ? no output loads on gate drive pins, no pwm ? no output loads on gate drive pins, 20 khz, 50% duty cycle C C 1.0 C C 10 ma i pwr_on vpwr supply current, v pwr = v sup = 40 v rst and enable = 5.0 v ? no output loads on gate drive pins, no pwm, outputs initializ ed ? output loads = 620 nc per fet, 20 khz pwm C C 11 C 20 95 ma (11) i sup i pwr sleep state supply current, rst = 0 v ? v sup = 40 v ? v pwr = 40 v C C 14 56 30 100 a v gatess sleep state output gate voltage ? ig < 100 a C C 1.3 v v boot trickle charge pump (bootstrap voltage, v sup = 14 v 22 28 32 v (12) v f bootstrap diode forward voltage at 10 ma C C 1.2 v vdd internal regulator v dd v dd output voltage, v pwr = 8.0 v to 40 v, c = 0.47 f ? external load i dd_ext = 0 ma to 1.0 ma 4.5 C 5.5 v (13) i dd internal v dd supply current, v dd = 5.5 v, no external load C C 12 ma vls regulator i peak peak output current, v pwr = 16 v, v ls = 10 v 350 600 800 ma v ls linear regulator output voltage, i vls = 0 ma to 60 ma, v pwr > v ls + 2.0 v 13.5 15 17 v (14) v thvls vls disable threshold 7.5 8.0 8.5 v (15) notes 10. operation with the charge pump is recommended when minimum s ystem voltage could be less than 14 v. v pwr must exceed this threshold in order for the charge pump and v dd regulator to startup and drive v pwr to > 8.0 v. once v pwr exceeds 8.0 v, the circui ts continue to operate even if system voltage drops below 6.0 v. 11. this parameter is guaranteed by design. it is not production tested. 12. see figure 11 for typical capability to maintai n gate voltage with a 5.0 a load. 13. minimum external capacitor for stable v dd operation is 0.47 f. 14. recommended external capacitor for the v ls regulator is 2.2 f low esr at each pin vls and vls_cap. 15. when v ls is less than this value, the outputs are disabled and holdoff circuits are active. recovery requires initialization when v ls rises above this threshold again. a filter delay of approximately 700 ns on the comparator output eliminates responses to spurious transie nts on v ls .
analog integrated circuit device data 10 nxp semiconductors 33gd3000 charge pump r ds(on)_hs r ds(on)_ls v threg charge pump ? high-side switch on resistance ? low-side switch on resistance ? regulation threshold difference C C 250 6.0 5.0 500 10 9.4 900 mv (16) , (17) v cp charge pump output voltage ? i out = 40 ma, 6.0 v < v sys < 8.0 v ? i out = 40 ma, v sys > = 8.0 v 8.5 12 9.5 C C C v (17) , (18) gate drive r ds(on)_h_src high-side driver on resistance (sourcing) ? v pwr = v sup = 16 v, - 40 c t a 25 c ? v pwr = v sup = 16 v, 25 c < t a 125 c C C C C 6.0 8.5 r ds(on)_h_sink high-side driver on resistance (sinking) ? v pwr = v sup = 16 v C C 3.0 i hs_inj high-side current injection al lowed without malfunction C C 0.5 a (17) , (19) r ds(on)_l_src low-side driver on resistance (sourcing) ? v pwr = v sup = 16 v, - 40 c t a 25 c ? v pwr = v sup = 16 v, 25 c < t a 125 c C C C C 6.0 8.5 r ds(on)_l_sink low-side driver on-resistance (sinking) ? v pwr = v sup = 16 v C C 3.0 i ls_inj low-side current injection al lowed without malfunction C C 0.5 (17) , (19) v gs_h v gs_l gate source voltage, v pwr = v sup = 40 v ? high-side, i gate = 0 ? low-side, i gate = 0 13 13 14.8 15.4 16.5 17 v (20) v hs_g_hold reverse high-side gate holding voltage ? gate output holding current = 2.0 a ? gate output holding current = 5.0 a, v sup <26 v ? gate output holding current = 5.0 a, v sup <40 v C C C 10 10 C 15 15 15 v (21) notes 16. when vls is this amount below the normal vls linear regulati on threshold, the charge pump is enabled. 17. this parameter is a design c haracteristic, not production te sted. 18. v sys is the system voltage on the input to the charge pump. recomme nded external components: 1.0 f mlc, mur 120 diode. 19. current injection only occurs during output switch transitio ns. the ic is immune to specified injected currents for a durat ion of approximately 1.0 s after an output switch transition . 1.0 s is sufficient for all intended applications of this ic. 20. if a slightly higher gate vo ltage is required, larger bootst rap capacitors are required. a t high duty cycles, the bootstrap voltage may not recover completely, leading to a higher output on-resistance. this effe ct can be minimized by using low esr capacitors for the bootstr ap and the vls capacitors. 21. high-side gate holding voltage is the voltage between the ga te and source of the high-side fet when held in an on condition . the trickle charge pump supplies bias and holding cu rrent for the high-side fet ga te driver and output to maintain voltages after bootstrap event s. see figure 11 for typical 100% high-side gate voltage with a 5.0 a load. thi s parameter is a design characte ristic, not production tested. table 4. static e lectrical characteristics (continued) characteristics noted under conditions 8.0 v v pwr = v sup 40 v , - 40 c t a 125 c, unless otherwise not ed. typical values noted reflect the approximat e parameter means at t a = 25 c under nominal condition s, unless otherwise noted. symbol characteristic min. typ. max. unit notes
analog integrated circuit device data nxp semiconductors 11 33gd3000 overcurrent comparator v cm common mode input range 2.0 C v dd -0.02 v (22) v os_oc input offset voltage -50 C 50 mv v oc_hyst overcurrent comparator threshold hysteresis 50 300 mv (23) v oh v ol output voltage ? high level at i oh = -500 a ? low level at i ol = 500 a 0.85 v dd C C C v dd 0.5 v hold off circuit i hold hold off current (at each gate pin) ? 3.0 v < v sup < 40 v, v gate = 1.0 v 10 C 300 a (24) phase comparator v ih_th high level input voltage threshold 0.5 v sup C 0.65 v sup v v il_th low level input voltage threshold 0.3 v sup C 0.45 v sup v v oh high level output voltage at i oh = -500 a 0.85 v dd C v dd v v ol low level output voltage at i ol = 500 a C C 0.5 v r in high-side source input resistance C 40 C k (23) , (25) desaturation detector v des_th desaturation detector threshold 1.2 1.4 1.6 v (26) current sense amplifier r s recommended external series resistor (see figure 9 ) C 1.0 C k r fb recommended external feedback resistor (see figure 9 ) ? limited by the output voltage dynamic range 5.0 C 15 k (27) v id maximum input differential voltage (see figure 9 ) ? v id = v amp_p - v amp_n -800 C +800 mv v cm input common mode range -0.5 C 3.0 v (23) , (28) v os input offset voltage ? r s = 1.0 k , v cm = 0.0 v -15 C +15 mv v os / t input offset voltage drift C -10 C v/c (23) i b input bias current ? v cm = 2.0 v -200 C +200 na notes 22. as long as one input is in the common mode range there is no phase inversion on the output. 23. this parameter is a design ch aracteristic, not production te sted. 24. the hold off circuit is designed to operate over the full op erating range of v sup . the specification indicates the conditions used in production test. hold off is activated at v por or v thvls. 25. input resistance is impedanc e from the high-side source and is referenced to v ss . approximate tolerance is 20 %. 26. desaturation is measured as the voltage drop below v sup , thus the threshold is compared to the drain-source voltage of the external high-side fet. see figure 5 . 27. the current sense amplifier is unity gain stable with a phas e margin of approximately 45. see figure 10 . 28. as long as one input is within v cm the output is guaranteed to have the correct phase. exceeding the common mode rails on one input does not cause a phase inversion on the output. table 4. static electrical characteristics (continued) characteristics noted under conditions 8.0 v v pwr = v sup 40 v , - 40 c t a 125 c, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditi ons, unless otherwise noted. symbol characteristic min. typ. max. unit notes
analog integrated circuit device data 12 nxp semiconductors 33gd3000 current sense amplifier (continued) i os input offset current ? i os = i amp_p - i amp_n -80 C +80 na i os / t input offset current drift C 40 C pa/c (29) v oh v ol output voltage ? high level with r load = 10 k to v ss ? low level with r load = 10 k to v dd v dd -0.2 C C C v dd 0.2 v r i differential input resistance 1.0 C C m i sc output short-circuit current 5.0 C C ma c i common mode input capacitance at 10 khz C C 10 pf (29) , (30) c mrr common mode rejection ratio at dc ? cmrr = 20*log ((v out_diff /v in _ diff ) * (v in _ cm /v out _ cm )) 60 80 C db a ol large signal open loop voltage gain (dc) C 78 C db (29) , (30) nl nonlinearity ? rl = 1.0 k , c l = 500 pf, 0.3 < v o < 4.8 v, gain = 5.0 to 15 -1.0 C +1.0 % (29) , (30) supervisory and control circuits v ih v il logic inputs (px_ls, px_hs , en1, en2) ? high level input voltage threshold ? low level input voltage threshold 2.1 C C C C 0.9 v (31) v ih v il logic inputs (si, sclk, cs ) ? high level input voltage threshold ? low level input voltage threshold 2.1 C C C C 0.9 v (31) , (32) v ihys input logic threshold hysteresis ? inputs px_ls, si, sclk, cs , px_hs , en1, en2 100 250 450 mv (32) i inpd input pull-down current, (px_ls, si, sclk, en1, en2) ? 0.3 v dd v in v dd 8.0 C 18 a i inpu input pull-up current, (cs , px_hs ) ? 0 v in 0.7 v dd 10 C 25 a (33) c in input capacitance ? 0.0 v v in 5.5 v C 15 C pf (32) v th_rst rst threshold 1.0 C 2.1 v (34) r rst rst pull-down resistance ? 0.3 v dd v in v dd 40 60 85 k v por power-off rst threshold, (v dd falling) 3.4 4.0 4.5 v v soh so high level output voltage ? i oh = 1.0 ma 0.9 v dd C C v v sol so low level output voltage ? i ol = 1.0 ma C C 0.1 v dd v notes 29. this parameter is a design c haracteristic, not production te sted. 30. without considering any offset s such as input offset voltage , internal mismatch and assuming no tolerance error in external resistors. 31. logic threshold voltages derived relative to a 3.3 v 10% sys tem. 32. this parameter is guaranteed by design, not production teste d. 33. pull-up circuits do no t allow back biasing of v dd. 34. there are two elements in the rst circuit: 1) one generally lower threshold enables the internal regulator; 2) the second removes the reset from the internal logic. table 4. static e lectrical characteristics (continued) characteristics noted under conditions 8.0 v v pwr = v sup 40 v , - 40 c t a 125 c, unless otherwise not ed. typical values noted reflect the approximat e parameter means at t a = 25 c under nominal condition s, unless otherwise noted. symbol characteristic min. typ. max. unit notes
analog integrated circuit device data nxp semiconductors 13 33gd3000 supervisory and control circuits i so_leak_t so tri-state leakage current ? cs = 0.7 v dd , 0.3 v dd v so 0.7 v dd -1.0 C 1.0 a c so_t so tri-state capacitance (35) , (36) ? 0.0 v v in 5.5 v C 15 C pf v oh int high level output voltage ? i oh = -500 a 0.85 v dd C v dd v v ol int low level output voltage ? i ol = 500 a C C 0.5 v thermal warning t warn thermal warning temperature (35) , (37) 150 170 185 c t hyst thermal hysteresis (35) 8.0 10 12 c notes 35. this parameter is guaranteed by design, not production teste d. 36. this parameter applies to the off state (tri-stated) conditi on of so is guaranteed by design but is not production tested. 37. the thermal warning circuit does not force ic shutdown above this temperature. it is possible to set a bit in the mask regi ster to generate an interrupt when overtemperature is detected, and the status bit always indicates if any of the three individual thermal warning circuits in the ic sense a fault. table 4. static electrical characteristics (continued) characteristics noted under conditions 8.0 v v pwr = v sup 40 v , - 40 c t a 125 c, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditi ons, unless otherwise noted. symbol characteristic min. typ. max. unit notes
analog integrated circuit device data 14 nxp semiconductors 33gd3000 4.3 dynamic electrical characteristics table 5. dynami c electrical char acteristics characteristics noted under conditions 8.0 v v pwr = v sup 40 v, - 40 c t a 125 c, unless otherwise noted. typical values noted reflect the approximat e parameter means at t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min. typ. max. unit notes internal regulators t pu_vdd v dd power-up time (until int high) ? 8.0 v v pwr C C 2.0 ms (38) , (39) t pu_vls vls power-up time ? 16 v v pwr C C 2.0 ms (39) , (40) charge pump f osc charge pump oscillator frequency 90 125 190 khz sr cp charge pump slew rate C 100 C v/s (41) gate drive t onh high-side turn on time ? transition time from 1.0 v to 10 v, load: c = 500 pf, rg = 0, ( figure 7 ) C 20 35 ns (42) t d_onh high-side turn on delay ? delay from command to 1.0 v, ( figure 7 ) 130 265 386 ns (43) t offh high-side turn off time ? transition time from 10 v to 1.0 v, load: c = 500 pf, rg = 0, ( figure 8 ) C 20 35 ns (42) t d_offh high-side turn off delay ? delay from command to 10 v, ( figure 8 ) 130 265 386 ns (43) t onl low-side turn on time ? transition time from 1.0 v to 10 v, load: c = 500 pf, rg = 0, ( figure 7 ) C 20 35 ns (42) t d_onl low-side turn on delay ? delay from command to 1.0 v, ( figure 7 ) 130 265 386 ns (43) t offl low-side turn off time ? transition time from 10 v to 1.0 v, load: c = 500 pf, rg = 0, ( figure 8 ) C 20 35 ns (42) t d_offl low-side turn off delay ? delay from command to 10 v, ( figure 8 ) 130 265 386 ns (43) t d_diff same phase command delay match -20 0.0 +20 ns (44) t dur thermal filter duration 8.0 C 30 s (45) notes 38. the power-up time of the ic depends in part on the time requ ired for this regulator to charge up the external filter capaci tor on v dd . 39. this specification is based on capacitance of 0.47 f on vdd , 2.2 f on vls and 2.2 f on vls_cap. 40. the power-up time of the ic depends in part on the time requ ired for this regulator to charge up the external filter capaci tors on vls and vls_cap. this delay includes t he expected time for v dd to rise. 41. the charge pump operating at 12 v v sys , 1.0 f pump capacitor, mur120 diodes and 47 f filter capacitor. 42. this parameter is guaranteed by characterization, not produc tion tested. 43. these delays include all logi c delays except deadtime. all i nternal logic is synchronous with the internal clock. the total delay includes one clock period for state machine decisi on block, an additional clock pe riod for fullon mux logic, input synchronization time and outpu t driver propagation delay. subtract one clock period for operation in fullon mode w hich bypasses the state machine decision block. synchronization time accounts for up to one clock period of variation. see figure 6 . 44. the maximum separation or overlap of the high and low-side g ate drives, due to propagation delays when commanding one on an d the other off simultaneously, is guaranteed by design. 45. the output of the overtemperature comparator goes through a digital filter before generating a warning or interrupt.
analog integrated circuit device data nxp semiconductors 15 33gd3000 gate drive (continued) t dc duty cycle 0.0 C 96 % (46) , (47) t dc 100% duty cycle duration C C unlimited s (46) , (47) t max maximum programmable deadtime 10.2 15 19.6 s (48) overcurrent comparator t oc overcurrent protection filter time 0.9 C 3.5 s t roc rise time (oc_out) ? 10% - 90%, c l = 100 pf 10 C 240 ns t foc fall time (oc_out) ? 90% - 10%, c l = 100 pf 10 C 200 ns desaturation detector and phase comparator t r t f phase comparator propagation delay time to 50% of v dd ; c l 100 pf ? rising edge delay ? falling edge delay C C C C 200 350 ns t match phase comparator match (prop delay mismatch of three phases) ? c l = 100 pf C C 100 ns (46) t blank desaturation and phase error blanking time 4.7 7.1 9.1 s (49) t filt desaturation filter time ( filter time is digital) ? fault must be presen t for this time to trigger 640 937 1231 ns (46) current sense amplifier t settle output settle time to 99% ? rl = 1.0 k , c l = 500 pf, 0.3 v < v o < 4.8 v, gain = 5 to 15 C 1.0 2.0 s (46) , (50) t is_rise output rise time to 90% ? rl = 1.0 k , c l = 500 pf, 0.3 v < v o < 4.8 v, gain = 5.0 to 15 C C 1.0 s (51) t is_fall output fall time to 10% ? rl = 1.0 k , c l = 500 pf, 0.3 v < v o < 4.8 v, gain = 5.0 to 15 C C 1.0 s (51) sr 5 slew rate at gain = 5.0 ? rl = 1.0 k , c l = 20 pf 5.0 C C v/s (46) f m phase margin at gain = 5.0 C 30 C (46) notes 46. this parameter is guaranteed by design, not production teste d. 47. as duty cycle approaches the limit of 100% or 0% there is a maximum and minimum which is not achievable due to deadtime, pr opagation delays, switching times and charge time of the bootstrap capacitor (for the high-side fet). 0% is avail able by definition (fet always off) and unlimited on (100%) is possible as long as gate charge maintenance curren t is within the trickle charge pump capacity. 48. a minimum deadtime of 0.0 can be set via an spi command. whe n deadtime is set via a deadtime command, a minimum of 1 clock cycle duration and a maximum of 255 cl ock cycles is set usi ng the internal tim e base clock as a reference. c ommands exceeding this value limi ts at this value. 49. blanking time, t blank , is applied to all phases simul taneously when switching on any output fet. this precludes false errors due to system noise during the switching event. 50. without considering any offset s such as input offset voltage , internal mismatch and assuming no tolerance error in external resistors. 51. rise and fall times are measur ed from the transition of a st ep function on the input to 90% of the change in output voltage . table 5. dynamic electrical characteristics (continued) characteristics noted under conditions 8.0 v v pwr = v sup 40 v, - 40 c t a 125 c, unless otherwise not ed. typical values noted reflect the approximate parameter means at t a = 25 c under nominal condition s, unless otherwise noted. symbol characteristic min. typ. max. unit notes
analog integrated circuit device data 16 nxp semiconductors 33gd3000 current sense amplifier (continued) g bw unity gain bandwidth ? rl = 1.0 k , c l = 100 pf C20Cmhz (52) bw g bandwidth at gain = 15 ? r l = 1.0 k , c l = 50 pf 2.0 C C mhz (52) cmr common mode rejection (cmr) with v in ? v in_cm = 400 mv*sin(2* *freq*t) ? v in _ dif = 0.0 v, rs = 1.0 k ? r fb = 15 k , v refin = 0.0 v cmr = 20*log(v out /v in _ cm ) ? freq = 100 khz ? freq = 1.0 mhz ? freq = 10 mhz 50 40 30 C C C C C C db (52) supervisory and control circuits t prop en1 and en2 propagation delay C C 280 ns t rint int rise time cl = 100 pf 10 C 250 ns t fint int fall time cl = 100 pf 10 C 200 ns t propint int propagation time C C 250 ns t trrst rst transition time (rise and fall) C C 1.25 s (52) , (53) spi interface timing f op maximum frequency of spi operation C 4.0 mhz f tb internal time base 13 17 25 mhz tc tb internal time base drift from value at 25 c -5.0 C 5.0 % (52) t lead falling edge of cs to rising edge of sclk (required setup time) 100 C C ns (52) t lag falling edge of sclk to rising edge of cs (required setup time) 100 C C ns (52) t sisu si to falling edge of sclk (required setup time) 25 C C ns (52) t sihold falling edge of sclk to si (required setup time) 25 C C ns (52) t rsi si, cs , sclk signal rise time C 5.0 C ns (52) , (54) t fsi si, cs , sclk signal fall time C 5.0 C ns (52) , (54) t soen time from falling edge of cs to so low-impedance C 55 100 ns (52) , (55) t sodis time from rising edge of cs to so high-impedance C 100 125 ns (52) , (56) t valid time from rising edge of sclk to so data valid C 80 125 ns (52) , (57) t dt time from rising edge of cs to falling edge of the next cs 200 C C ns (52) notes 52. this parameter is guaranteed by design, not production teste d. 53. t trrst is given as a design guideli ne. the bounds for this specificat ion are vpwr 58 v, total capacitance on vls > 1.0 f. 54. rise and fall time of incoming si, cs , and sclk signals suggested for design consideration to preven t the occurrence of double pulsing. 55. time required for valid output status data to be available o n so pin. 56. time required for output states data to be terminated at so pin. 57. time required to obtain vali d data out from so following the rise of sclk with 200 pf load. table 5. dynamic el ectrical characteri stics (continued) characteristics noted under conditions 8.0 v v pwr = v sup 40 v, - 40 c t a 125 c, unless otherwise noted. typical values noted reflect the approximat e parameter means at t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min. typ. max. unit notes
analog integrated circuit device data nxp semiconductors 17 33gd3000 4.4 timing diagrams figure 4. spi interface timing figure 5. desaturation bla nking and filtering detail figure 6. deadtime control delays t do (dis) 0.7 v dd 0. 2 v dd 0.2 v dd 0.7 v dd 0.2 v dd t lead t di(su) t di(ho ld) t valid t lag cs sclk si so msb in msb out lsb out 0.7 v dd 0.2 v dd t do(en) t sodis t soen t sisu t sihold t lag from delay timer p x _hs p x _ls desaturation fault p x _ls p x _hs en1 en2 rst state deadtime control 1 st pulse machine p x _hs_g p x _hs_s p x _ls_g dq clk d q clk dq clk dq clk dq clk dq clk b out a mux b out a mux
analog integrated circuit device data 18 nxp semiconductors 33gd3000 figure 7. driver turn-on time and turn-on delay figure 8. driver turn-off time and turn-off delay 50 % px_hs _g px_hs 10v 1.0v t d_onh t onh 50% px_ls_g px_ls 10v 1.0v t d_onl t onl 50% 10v 1.0v t d_offl t offl px_ls_g px_ ls px_hs_g px_hs 50% 10v 1.0v t d_offh t offh
analog integrated circuit device data nxp semiconductors 19 33gd3000 figure 9. current amplifier and input waveform (v in voltage across r sense ) figure 10. typical amplifier op en-loop gain and phase vs. freq uency v in - ref r sense amp_out amp_p amp_n oc_th v id r f bn r fb p r s r s + + - to protection circuits 0v 0v -400mv to + 400mv -400mv to + 400mv 0.5s - 50s 0.5s - 50s 0s - 0.5s gain (db) phase (degrees) gain phase
analog integrated circuit device data 20 nxp semiconductors 33gd3000 figure 11. typical high-side 100% on gate voltage with 5.0 a gate load 16 typical high side 100% on gate voltage with 5 p a gate load v sup = 40v 14 v sup = 24v sup 10 12 v sup = 9v v sup = 14v 8 v cboot r v hs_s (v) 4 6 2 0 r 50 r 30 r 10 10 30 50 70 90 110 130 150 temperature (c)
analog integrated circuit device data nxp semiconductors 21 33gd3000 5 functional descriptions 5.1 introduction the 33gd3000 provides an interface between an mcu and the large fets used to drive three phase loads. a typical load fet may h ave an on resistance of 4.0 m or less and could require a gate charge of over 400 nc to full y turn on. the ic can operate in automotive 12 v to 42 v environments. because there are so many methods of controlling three phase sy stems, the ic enforces few constr aints on driving the fets. it does provide deadtime (cross-over) bl anking and logic, both of which can be overridden, ensuring both fets in a phase are not simul taneously enabled. an spi port is used to configure the ic modes. 5.2 functional pin description 5.2.1 phase a (phasea) this pin is the totem pole output of the phase a comparator. th is output is low when the voltage on phase a high-side source ( source of the high-side load fet) is less than 50 percent of v sup . 5.2.2 power ground (pgnd) this pin is power ground for the charge pump. it should be conn ected to vss, however routing to a single point ground on the p cb may help to isolate charge pump noise. 5.2.3 enable 1 and enable 2 (en1, en2) both of these logic signal inputs must be high to enable any ga te drive output. when ei ther or both are low, the internal logi c (spi port, etc.) still functions normally, but all gate drives are forced off (external power fet gates pulled low). the signal is asynch ronous. when en1 and en2 return high to e nable the outputs, each ls dri ver must be pulsed on before th e corresponding hs driver can be commanded on. this ensures the b ootstrap capacitors are charged . see initialization re quirements on page 39 . 5.2.4 reset ( rst ) when the reset pin is low the integrated circuit (ic) is in a l ow power state. in this mode all outputs are disabled, internal bias circuits are turned off, and a small pull-down current is applied to the out put gate drives. the internal logic is reset within 77 ns of re set going low. when rst is low, the ic consum es minimal current. 5.2.5 charge pump out (pump) this pin is the switching node of the charge pump circuit. the output of the internal charge pump support circuit. when the ch arge pump is used, it is connected to the external pumping capacitor. thi s pin may be left floating if t he charge pump is not required. 5.2.6 charge pump input (vpump) this pin is the input supply for the charge pump c ircuit. when the charge pump is required, this pin should be connected to a polarity protected supply. this input shou ld never be connected to a sup ply greater than 40 v. if the char ge pump is not required this pin may be left floating. 5.2.7 vsup input (vsup) the supply voltage pin should be connected to the common connec tion of the high-side fets. it is the reference bias for the ph ase comparators and desat uration comparator. it is also used to pro vide power to the inte rnal steady state tri ckle charge pump and to energize the hold off circuit.
analog integrated circuit device data 22 nxp semiconductors 33gd3000 5.2.8 phase b (phaseb) this pin is the totem pole output of the phase b comparator. th is output is low when the voltage on phase b high-side source ( source of the high-side load fet) is less than 50 percent of v sup . 5.2.9 phase c (phasec) this pin is the totem pole output of the phase c comparator. th is output is low when the voltage on phase c high-side source ( source of the high-side load fet) is less than 50 percent of v sup . 5.2.10 phase a high-side input ( pa_hs ) this input logic signal pin enables the high-side driver for ph ase a. the signal is active low, and is pulled up by an interna l current source. 5.2.11 phase a low-side input (pa_ls) this input logic signal pin enables the low-side driver for pha se a. the signal is active high, and is pulled down by an inter nal current sink. 5.2.12 vdd voltage regulator (vdd) vdd is an internally generated 5.0 v supply. the internal regul ator provides continuous power to the ic and is a supply refere nce for the spi port. a 0.47 f (min.) decoupling capacitor must be connect ed to this pin. this regulator is intended for internal ic use and can supply only a small (1.0 ma) e xternal load current. a power-on-reset (por) circuit monitors this pin and until the voltage rises above the threshol d, the internal logic resets; d river outputs are tri-stated, and spi communication disabled. the vdd regulat or can be disabled by asserting the rst signal low. the vdd regulator is powered from the vpwr pin. 5.2.13 phase b high-side control input ( pb_hs ) this pin is the input logic signal, enabling the high-side driv er for phase b. the signal is active low, and is pulled up by a n internal current source. 5.2.14 phase b low-side input (pb_ls) this pin is the input logic signal, enabling the low-side drive r for phase b. the signal is active high, and is pulled down by an internal current sink. 5.2.15 interrupt (int) the interrupt pin is a totem pole logic output. when a fault is detected, this pin pulls high un til it is cleared by executing the clear interrupt command via the spi p ort. the faults capable of causing an inte rrupt can be masked via the mask0 and mask1 spi registers to customize the response. 5.2.16 chip select ( cs ) chip select is a logic input wh ich frames the spi commands and enables the spi port. this signal is active low, and is pulled up by an internal current source. 5.2.17 serial in (si) the serial in pin is used to in put data to the spi port. clocke d on the falling edge of sclk, it is the most significant bit ( msb) first. this pin is pulled down by an internal current sink.
analog integrated circuit device data nxp semiconductors 23 33gd3000 5.2.18 serial clock (sclk) this logic input is the clock is used for the spi port. the scl k typically runs at 3.0 mhz (up to 5.0 mhz) and is pulled down by an internal current sink. 5.2.19 serial out (so) output data for the spi port streams from this pin. it is tri-s tated until cs is low. new data appears on rising edges of sclk in preparatio n for latching by the falling edge of sclk on the master. 5.2.20 phase c low-side input (pc_ls) this input logic pin enables the low-side driver for phase c. t his pin is an active h igh, and is pulled do wn by an internal cu rrent sink. 5.2.21 phase c high-side input ( pc_hs ) this input logic pin enables the high-side driver for phase c. this signal is active low, and i s pulled up by an internal curr ent source. 5.2.22 amplifier output (amp_out) this pin is the output for the current sensing amplifier. it is also the sense input to t he overcurrent comparator. 5.2.23 amplifier inverting input (amp_n) the inverting input to the current sensing amplifier. 5.2.24 amplifier non-inverting input (amp_p) the non-inverting input to the current sensing amplifier. 5.2.25 overcurrent compa rator output (oc_out) the overcurrent comparator outpu t is a totem pole logic level o utput. a logic high indicates an overcurrent condition. 5.2.26 overcurrent comparator threshold (oc_th) this input sets the threshold le vel of the overcurrent comparat or. 5.2.27 voltage source supply (vss) vss is the ground reference for the logic interface and power s upplies. 5.2.28 ground (gnd0,gnd1) these two pins are connected internally to vss by a 1.0 resistor. they provide device substrate connections and also t he primary return path for esd protection. 5.2.29 vls regulator capacitor (vls_cap) this connection is for a capacitor which provides a low-impedan ce for switching curr ents on the gate drive. a low esr decoupli ng capacitor, capable of sourcing t he pulsed drive currents must b e connected between this pin and vss. this is the same dc node as vls, but it is physically placed on the opposite end of the ic to minimize the source impedance to the gate drive circuits.
analog integrated circuit device data 24 nxp semiconductors 33gd3000 5.2.30 phase c low-side source (pc_ls_s) the phase c low-side source is the pin used to return the gate currents from the low-side fet. best performance is realized by connecting this node directly to the source of the low-side fet for phase c. 5.2.31 phase c low-side gate (pc_ls_g) this is the gate drive for the phase c low-side output fet. it provides high-current through a low-impedance to turn on and of f the low- side fet. a low-impedance drive ensures transient currents do n ot overcome an off-state driver and allow pulses of current to flow in the external fet. this output has al so been designed to resist the influence of nega tive currents. 5.2.32 phase c high-side source (pc_hs_s) the source connection for the phase c high-side output fet is t he reference voltage for the gate drive on the high-side fet an d also the low-voltage end of the bootstrap capacitor. 5.2.33 phase c high-side gate (pc_hs_g) this is the gate drive for the p hase c high-side output fet. th is pin provides the ga te bias to turn the ex ternal fet on or of f. the gate voltage is limited to about 15 v above the fet source voltage. a low-impedance drive is used, ensuring transient currents do n ot overcome an off-state driver and allow pulses of cu rrent to flow in the external fets. this output has a lso been designed to resist the influence of negative currents. 5.2.34 phase c bootstrap (pc_boot) this is the bootstrap capacitor connection for phase c. a capac itor connected between pc_hs_s a nd this pin provides the gate v oltage and current to drive the external fet gate. typically, the boot strap capacitor selection is 10 to 20 times the gate capacitanc e. the voltage across this capacitor i s limited to about 15 v. 5.2.35 phase b low-side source (pb_ls_s) the phase b low-side source is the pin used to return the gate currents from the low-side fet. best performance is realized by connecting this node directly to the source of the low-side fet for phase b. 5.2.36 phase b low-side gate (pc_ls_g) this is the gate drive for the p hase b low-side output fet. it provides high-current through a low-impedance to turn on and of f the low- side fet. a low-impedance drive ensures transient currents do n ot overcome an off-state driver and allow pulses of current to flow in the external fet. this output has al so been designed to resist the influence of nega tive currents. 5.2.37 phase b high-side source (pb_hs_s) the source connection for the phase b high-side output fet is t he reference voltage for the gate drive on the high-side fet an d also the low-voltage end of the bootstrap capacitor. 5.2.38 phase b high-side gate (pb_hs_g) this is the gate drive for the p hase b high-side output fet. th is pin provides the gat e bias to turn the e xternal fet on or of f. the gate voltage is limited to about 15 v above the fet source voltage. a low-impedance drive is used, ensuring transient currents do n ot overcome an off-state driver and allow pulses of cu rrent to flow in the external fets. this output has a lso been designed to resist the influence of negative currents. 5.2.39 phase b bootstrap (pb_boot) this is the bootstrap capacitor connection for phase b. a capac itor connected between pc_hs_s and this pin provides the gate v oltage and current to drive the external fet gate. typically, the boot strap capacitor selection is 10 to 20 times the gate capacitanc e. the voltage across this capacitor i s limited to about 15 v.
analog integrated circuit device data nxp semiconductors 25 33gd3000 5.2.40 phase a low-side source (pa_ls_s) the phase a low-side source is the pin used to return the gate currents from the low-side fet. best performance is realized by connecting this node directly to the source of the low-side fet for phase a. 5.2.41 phase a low-side gate (pa_ls_g) this is the gate drive for the phase a low-side output fet. it provides high-current through a low-impedance to turn on and of f the low- side fet. a low-impedance drive ensures transient currents do n ot overcome an off-state driver and allow pulses of current to flow in the external fet. this out put has also been des igned to resist the influence of negative currents. 5.2.42 phase a high-s ide source (pa_hs_s) the source connection for the phase a high-side output fet is t he reference voltage for the gate drive on the high-side fet an d also the low-voltage end of the bootstrap c apacitor. 5.2.43 phase a high-side gate (pa_hs_g) this is the gate drive for the phase a high-side output fet. th is pin provides the gate bias to turn the external fet on or of f. the gate voltage is limited to about 15 v above the fet source voltage. a low-impedance drive is used, e nsuring transient currents do n ot overcome an off-state driver and allow pulses of current to flo w in the external fets. this ou tput has also been designed to r esist the influence of negative currents. 5.2.44 phase a bootstrap (pa_boot) this is the bootstrap capacitor c onnection for phase a. a capac itor connected between pc_hs_s and this pin provides the gate v oltage and current to drive the external fet gate. typically, the boot strap capacitor selection is 10 to 20 times the gate capacitanc e. the voltage across this capacitor is limited to about 15 v. 5.2.45 vls regulator (vls) vls is the gate drive power supply regulated at approximately 1 5 v. this is an internally gener ated supply from vpwr. it is th e source for the low-side gate drive volt age, and also the high-side boo tstrap source. a low esr decoupl ing capacitor, capable of sourc ing the pulsed drive currents, must be co nnected between t his pin and v ss. 5.2.46 vpwr input (vpwr) vpwr is the power supply input for vls and vdd. current flowing into this input recharges the bootstrap capacitors as well as supplying power to the low-side gate drive rs and the vdd r egulator. an in ternal regulator regulates the a ctual gate voltage s. this pin c an be connected to system battery volt age if power dissipation is not a concern. 5.2.47 exposed pad (ep) the primary function of the ex posed pad is to conduct heat out of the device. this pad may be connected el ectrically to the su bstrate of the device.the device performs as specified with the exposed pa d un-terminated (floating). however, it is recommended the expo sed pad be terminated to pin 29 ( vss) and the system ground.
analog integrated circuit device data 26 nxp semiconductors 33gd3000 6 functional internal block description figure 12. functional internal block description all functions of the ic can be described as the following five major functional blocks: ? logic inputs and interface ? bootstrap supply ? low-side drivers ? high-side drivers ? charge pump 6.1 logic inputs and interface this section contains the spi por t, control logic, and shoot-th rough timers. the ic logic inputs have schmitt trigger inputs w ith hysteresis. logic inputs are 3.0 v compatible. the logic outputs are driven from the internal supply of approximately 5.0 v. the spi registers and functionalit y is described completely in the logic commands and registers section of this document. spi functionality includes the following: ? programming of deadtime delay this delay is adjustable in approximately 50 ns steps from 0 ns to 12 s. calibration of the delay, because of internal ic variati ons, is performed via the spi. ? enabling of simultaneous operation of high-side and low-side fe ts normally, both fets would not be enabled simultaneously. however, for certain applications where the load is connected b etween the high-side and low-side fets, this could be advantage ous. if this mode is enabled, the blanking time delay is disabled. a sequence of commands may be required to enable this function t o prevent inadvertent enabling. in addition, this command can only be exe cuted once after reset to enable or disable simultaneous turn-o n. ? setting of various operating modes of the ic and enabling of interrupt sources. the 33gd3000 allows different ope rating modes to be set and loc ked by an spi comm and (fullon, desatur ation fault, zero deadtime). spi commands can also determine how the various faul ts are (or are n ot) reported. mc33gd3000 - functional block diagram integrated supply sensing & protection drivers high-side and low-side output pre-drivers logic & control integrated supply trickle charge pump 5.0 v regulator vls regulator main charge pump sensing & protection hold-off temperature current sense overcurrent de-sat phase undervoltage logic & control dead time fault register mode control phase control spi communication
analog integrated circuit device data nxp semiconductors 27 33gd3000 ? read back of internal registers . the status of the 33gd 3000 status registers can be read back by the master (dsp or mcu). the px_hs and px_ls logic inputs are edge s ensitive. this means the lead ing edge on an input causes t he complementar y output to immediately turn off a nd the selected one to turn on after the deadtime delay as illustrated in figure 13 . the deadtime delay timer always starts at the time a fet is com manded off and prevents the complementary fet from being comman ded on until after the deadtime has e lapsed. commands to turn on th e complementary fet after the d eadtime has elapsed are executed immediately without any further delay (see figure 6 and figure 13 ). figure 13. edge sensitive logic inputs (phase a) 6.1.1 low-side and bootstrap supply (vls) this is the portion of the ic providing current to recharge the bootstrap capacitors. it also s upplies the peak currents requi red for the low- side gate drivers. the power for t he gate drive circuits is pro vided by vls which is supplied from the vpwr pin. this pin can be connected to system battery voltage and i s capable of wit hstanding up to the full load dump v oltage of the syst em. however, the ic only requires a low-voltage supply on this pin, t ypically 13 to 1 6 v. higher vo ltages on this pin increases the ic power dissipation. in 12 v systems the supply volta ge can fall as low as 6.0 v. th is limits the gate voltage capable of being applied to the fets and reduces system performance due to the higher fet on-resistance. to allo w a higher gate voltage to be supplied, the ic also incorporate s a charge pump. the switches and control ci rcuitry are internal; the capa citors and diodes are external (see figure 22 ). 6.1.2 low-side drivers these three drivers turn on and off the external low-side fets. the circuits provide a low-impedance drive to the gate, ensuri ng the fets remain off in the presence of h igh dv/dt transients on their dr ains. additionally, these output drivers isolate the other port ions of the ic from currents capable of being in jected into the substrate due to rapid dv/dt transient s on the fet drains. low-side drivers switch power fro m vls to the gates of the low- side fets. the low-side drivers are capable of providing a typi cal peak current of 2.0 a. this gate dr ive current may be limited by ext ernal resistors in order to achie ve a good trade-off between th e efficiency and emc (electro-magnetic compati bility) compliance of the appl ication. the low-side driver use s high-side pmos for turn on an d low- side isolated ldmos for turn off . the circuit ensures the imped ance of the driver remains low, even during periods of reduced current. current limit is blanked immedia tely after subsequent input sta te change in order to ensure dev ice stays off du ring dv/dt tran sients. 6.1.3 high-side drivers these three drivers switch the voltage across the bootstrap cap acitor to the external high-side fets. the circuits provide a l ow-impedance drive to the gate, ensuring the fets remain off in the presence of high dv/dt transients on thei r sources. further, these outp ut drivers isolate the other portions of t he ic from currents capable of b eing injected into the substrate due to rapi d dv/dt transients on the fets. the high-side drivers deliver pow er from their bootstrap capaci tor to the gate of the external high-side fet, thus turning the high-side fet on. the high-side driver uses a level shifter, which allows the gate of the external high-side fet to be turned off by switchi ng to the high- side fet source. the gate supply voltage for the high-side drivers is obtained f rom the bootstrap supply, so, a short time is required after th e application of power to the ic to charge the bootstrap capacitors. to ensure t his occurrence, the internal control logic does not allow a hig h-side switch to be turned on after entering t he enable state un til the corre sponding low-side switch is enable d at least once. caution must be exercised after a long period o f inactivity of t he low-side swi tches to verify the bootstrap ca pacitor is not discharged. it i s charged by activating the low-side switches f or a brief peri od, or by atta ching external bleed resisto rs from the hs_s pins to gnd. see initialization requirements on page 39 . pa _h s pa_ls pa_ h s_ g pa_ls_g de adt ime de lay
analog integrated circuit device data 28 nxp semiconductors 33gd3000 in order to achieve a 100% duty cycle operation of the high-sid e external fets, a fully integrated trickle charge pump provide s the charge necessary to maintain the extern al fet gates at fully enhanced levels. the trickle charge pump has limited ability to supply e xternal leakage paths while performing its primary function. the graph in figure 11 shows the typical margin for supplying external current loads. these limits are based on maint aining the voltage at cboot at l east 3.0 v greater than the vo ltage on the hs_s for this phase. if this voltage differential becomes less than 3.0 v, the corresponding high-side fet most likely does not remain fully enhanced and t he high- side driver may malfunction due to insufficient bias voltage be tween cboot and hs_s. the slew rate of the external output fet is limited by the driv er output impedance, overall (ext ernal and internal) gate resis tance and the load capacitance. to ensure the low-side fet is not turned on b y a large positive dv/dt on the drain of the low-side fet, the turn-on slew rate of the high-side should be limited. if the slew rate of th e high-side is limited by the gat e-drain capacitance of the hig h-side fet, then the displacement current injecte d into the low-side gate drive output is approximately the same value. therefore, to ensure th e low-side drivers can be held off, the vo ltage drop across the low-side g ate driver must be lower than the threshold voltage of the low- side fet (see figure 14 ). similarly, during large negative dv/dt, the high-side fet is ab le to remain off if its gate drive low-side switch, develops a voltage drop less than the threshold voltage of the high-side fet. the gate drive low-side switch discharges the gate to the source. additionally, during negative dv /dt the low-side gate drive cou ld be forced below ground. the low -side fets must not inject de trimental substrate currents in this condition. the occurrence of these cases d epends on the polarity of the lo ad current during switching. figure 14. positive dv/dt transient 6.1.4 driver fault protection the 33gd3000 integrates several p rotection mechanisms against v arious faults. the first of them is the current sense amplifier with the overcurrent comparator. these two blocks are comm on for all thr ee driver phases. 6.1.4.1 current sense amplifier this amplifier is usually connect ed as a differential amplifier (see figure 9 ). it senses a current flowing th rough the external fets as a voltage across the current sense resistor r sense . since the amplifier common mode range does not extend below g round, it is necessary to use an external r eference to permit m easuring both positive and negative currents. the amplifier output can be moni tored directly (e.g. by the mic rocontrollers adc) at the amp_out pin, providing the means for closed loop control with the 33gd3000. th e output voltage is internall y compared with the overcurrent comparator threshold voltage (s ee figure 22 ). phase x output phase return px_ls_s px_ls_g px_hs_s low -si de driver ls control px_ls_g px_hs_g deadti me -v d v sup phase x output voltage dv/dt c gs c dg c ds r g i cdg vls 33927 + - g s d di scr ete fet package z o 33gd3000
analog integrated circuit device data nxp semiconductors 29 33gd3000 6.1.4.2 overcurrent comparator the amplified voltage across r sense is compared with the pre-set thr eshold value by the overcurren t comparator input. if the current sense amplifier output voltage e xceeds the threshold of the ove rcurrent comparator it would chang e the status of its output (o c_out pin) and the faul t condition woul d be latched (see figure 18 ). the occurrence of this fault would be signaled by the return va lue of the status register 0. if the proper interrupt mask has been set, this fault condition generates an int errupt - the int pin asserts hi gh. the int is held in the high state until the fault is remove d, and the appropriate bit in the status register 0 is cleared by the clin t0 command. this fault reporting technique is described in deta il in the logic commands and registers section. 6.1.4.3 desaturation detector the desaturation detector is a co mparator integrat ed into the o utput driver of each phase channe l. it provides an additional m eans to protect against short- to-ground fault condition. a short to g round is detected by an abnormally high-voltage drop in vds of the high- side fet. note that if the gate-s ource voltage of the high-side fet drops below saturation, the device goes into linear mode o f conduction which can also cause a desaturation error. figure 15. short to ground detection when switching from low-side to h igh-side, the high-side is com manded on after the e nd of the deadtime. the deadtime period st arts when the low-side is c ommanded off. if the voltage at px_hs_s i s less than 1 .4 v below v sup after the blanking time (t blank ) a desaturation fault is ini tiated. an additional 1.0 s digital filter is applied fr om the initiation of the desatura tion fault before i t is registered, and all phase drivers are turned off (px_hs_g clamped to px_hs_ s and px_ls_g clamped to px_ls_s ). if the desaturation fault condition clears before the filt er time expires, the fault is i gnored and the filt er timer resets. valid faults are registered in th e fault status register, which can be retrieved by way of the spi. additional spi commands ma sk the int flag and disable output stage shutdown, due to desaturation and phase errors. see logic commands and registers section for details on masking int behavior and disabling the protective function. v sup phase x output r sense phase return t- lim vls_cap px_ls_s px_ls_g px_hs_g px_hs_s px_boot phase comp. desat. comp. 3x + - vsup vsup 1.4v low -side dr iver hi gh -side dr iver hs control r r vls to curr ent sense amplif. phase x output shorted to ground (low-side fet shorted) ls control px_ls_g px_hs_g deadtime -v d v sup phase x output voltage shorted to ground correct phase x output voltage 0.5v sup phasex cor rec t fault phase error t blank t filt desaturation error
analog integrated circuit device data 30 nxp semiconductors 33gd3000 figure 16. short to supply detection 6.1.4.4 phase comparator faults could also be detected as phase errors . a phase error is generated if the output signal (at px_hs_s) do es not properl y reflect the drive conditions. a phase error is detected by a p hase comparator. the phase comp arator compares the voltage at the px_hs_s node with a referenc e of one half the voltage at the vsup pin. a high-side phase erro r (which also triggers the desaturation detector) occurs when t he high-side fet is commanded on, and px_hs_s is still low at the end of the deadtime and blanking time duration. similar ly, a ls phase error occurs when the low-side fet is comma nded on, and the px _hs_s is still high at the end of the deadtime a nd blanking time duration. the phase error flag is the tripl e or of phase errors from each phase. each phase e rror is the or of the high-side and low-sid e phase errors. this flag can generate an interrupt if the appropriate mask bit is set. the int is held in the high state until the fa ult is removed, and the appropriate bit in the status register 0 is cleared by the clint1 command. this f ault reporting mechanism is described in detail in the logic commands and registers section. 6.1.5 vls undervoltage since vls supplies both the gate driver circuits and the gate v oltage, it is critical it maintai ns sufficient potential to pla ce the power stage fets in saturation. since proper operation cannot continue with insufficient levels, a low vls condition shuts down driver ope ration. the vls under voltage threshold is between 7.5 v and 8.5 v. when a decreasing level reaches the thre shold, both the hs and the ls output gate circuit drive the gates off for about 8 us before reducing the drive to hold off levels. since low vls is a condition for turning on the hold off circuit, hold off then p rovides a weak pull-down on al l gates. a filter tim eout of about 700 ns ensures noise on vls does not cause premature protective action. when vls rises above this threshold again, the ls gate immediat ely follows the level of the input. however, a short initializa tion sequence must be executed to restore operation of the hs gate (see initialization requirements on page 39 ). since vls is no longer undervoltage, the hold off circuit is turned off and the hs gate is in a high -impedance state until the ls gat e responds to an input command to turn off. v sup phase x output r sense phase return t-lim vls_cap px_ls_s px_ls_g px_hs_g px_hs_s px_b oot phase comp. desat. comp. 3x + - vsup vsup 1. 4v low -side driver hi gh -side driver hs control r r vls to current sense amplif. phase x output shortedtov sup (high-side fet shorted) ls control px_ls_g px_hs_g deadtime -v d v sup phase x output voltage shorted to v sup correct phase x output voltage 0.5v sup phasex correct fault phase error t blank
analog integrated circuit device data nxp semiconductors 31 33gd3000 6.1.6 hold off circuit the ic guarantees the output fets are turned off in the absence of v dd or v pwr by means of the hold off circuit. a small current source, generated from vsup, typically 100 a, is mirrored and pulls al l the output gate drive pins low when v dd is less than about 3.0 v, rst is active (low), or when vls is lower than the vls_disable thresho ld. a minimum of 3.0 v is required on vsup to energize the hold off circuit. 6.1.7 charge pump the charge pump circui t provides the basic switching elements r equired to implement a charge p ump, when combin ed with external capacitors and diodes for enhanc ed low-voltage operation. when the 33gd3000 is connected per the typical application usin g the charge pump (see figure 22 ), the regulation path for vls includes the charge pump and a linear regulator. the regulation set poin t for the linear regulator is nominally at 15.34 v. as long as vls output voltage (vls out ) is greater than th e vls analog regulat or threshold (vls ath ) minus v threg , the charge pum p is not active. if vls out < vls ath C v threg the charge pump tu rns on until vls out > vls ath C v threg + v hyst. v hyst is approximately 200 mv. vls ath does not interfere wi th this cycle even wh en there is overlap in the thresholds, due to the des ign of the reg ulator system. the maximum current the charge pump can supply is dependent on the pump capacitor value and q uality, the pump frequency (nomin ally 130 khz), and the rdso n of the pump fe ts. the effective charge voltage for the pump capacitor would be v sys C 2 * v diode . the total charge transfer would then be c pump * (v sys C 2*v diode ). multiplying by the switch frequency gives the theoretical cu rrent the pump can transfer: f pump * c pump * (v sys C 2*v diode ). note: there is also another smaller, fully integrated charge pu mp (trickle charge pump - see figure 2 ), which is used to maintain the high-side drivers gate v gs in 100 percent duty cycle modes.
analog integrated circuit device data 32 nxp semiconductors 33gd3000 7 functional device operation 7.1 operational modes 7.1.1 reset and enable the 33gd3000 has three power modes of operation described in table 6 . there are three global control inputs (rst , en1, en2), which together with the stat us of vdd, vls and desat/phase faults con trol the behavior of the ic. the operating status of the ic can be descri bed by the followin g five modes: ? sleep mode - when rst is low, the ic is in sleep mode. the current consumption of th e ic is at minimum. ? standby mode - the rst input is high while one of the enable inputs is low. the ic is fully biased up and operating, all the external fets are actively turned off by both high-side and low-side gat e drives. the ic is ready to enter the enable mode. ? initialization mode - when en1, en2 and rst all go high, the device enters the initialization mode. toggli ng the ls and then the hs initializes the driver and no rmal operation in the enable mo de begins (see initialization requ irements on page 39 ). ? enable mode - after initialization is compl ete, the device goes into the e nable mode and operat es normally. normal operation continues in this mode as long as both enable pins and rst are high. ? fault protection mode - if a protective fault occurs (either desat/phase or vls uv) the device enters a fault protection mode. after a fault clears, the device requi res initialization again before resuming normal enable mode operation. table 6. functions of rst , en1 and en2 pins rst en1, en2 mode of operation (driver condition) 0xx sleep mode - in this mode (low quiescent current) the driver output stage is switched-off with a weak pull-down. all error and spi registers are cleared. the internal 5.0 v regulator is turned off and vdd is pulled low. all logic outp uts except so are clamped to vss. 1 0x x0 standby mode - ic fully biased up and all functions are operating, the outp ut drivers actively turn off al l of the external fets (after initialization). the spi port i s functional. logic level output s are driven with low-impedanc e. so is high-impedance unless cs is low. v dd , charge pump and v ls regulators are all operating. the ic is ready to move to enabl e mode. 111 initialization mode - low-side drivers are enabled, spi is fully operational. read y for initialization (see initialization requirements on page 39 ). enable mode - (normal operation). drivers are enabled; output stages follo w the input command. after enable, outputs require a pulse on px_ls before corresponding hs outputs turns on in orde r to charge the bootstrap capacitor. all error pin and register bits are active if detected. fault protection mode - drivers are turned off or disabled per the fault and protect ion mode registers. recovery requires initialization (see initialization requirements on page 39 ). table 7. functional ratings ( t j = -40 c to 150 c and supply voltage range v sup = v pwr = 5.0 to 45 v, c = 0.47 f) characteristic value default state of input pin px_ls, en1, en2, rst , si, sclk, if left open (58) (driver output is switc hed off, high-impedance mode) low (<1.0 v) default state of input pin px_hs , cs if left open (58) (driver output is switc hed off, high-impedance mode) high (>2.0 v) notes 58. to assure a defined status fo r all inputs, these pins are in ternally biased by pull-up/down current sources.
analog integrated circuit device data nxp semiconductors 33 33gd3000 figure 17. device ope rational flow diagram sleep mode initialization standby mode fault protection enable (normal) mode sleep rst n y stby en y n enable ls ls toggle hs toggle y ny n driver off disable driver desat/ vls uv y y n n enable hs desat vls uv en rst disabled n n n y y y y n y n holdoff active phase desat/ phase driver off
analog integrated circuit device data 34 nxp semiconductors 33gd3000 7.2 logic commands and registers 7.2.1 command descriptions the ic contains internal registers to control the various opera ting parameters, modes, and interrupt characteristics. these co mmands are sent and status is read via 8-bi t spi commands. the ic uses the last eight bits in an spi transfer, so devices can be daisy-ch ained. the first three bits in an spi word ca n be considered to be the com mand with the tra iling five bits be ing the data. the spi logic generates a frami ng error and ignor e the spi mess age if the number of received bits is not eight or if it is not a multiple of eight. after rst , the first spi result returned is status register 0. 7.2.2 fault reporting a nd interrupt generation different fault conditions descr ibed in the previous chapters c an generate an interr upt - int pin output s ignal asserted high. when an interrupt occurs, the source can be read fr om status register 0 , which is also the return word of most spi messages. faults ar e latched on occurrence, and the interrup t and faults are only cleared by sending the corresponding clint x command. a fault which still exists continues to asse rt an interrupt. note: if there are multiple pending interrupts, the int line do es not toggle when one of the faul ts is cleared. interrupt proc essing circuitry on the host must be leve l sensitive to correctly detect multipl e simultaneous interrupt. thus, when an interrupt occurs, the host can query the ic by se nding a null command; the return w ord contains flags indicating any faults not cleared since the clintx command was last written (r ising edge of cs ) and the beginning of the current spi command (falling edge of cs ). the null command c auses no changes to t he state of any of th e fault or mask bits. the logi c clearing the fault latches occurs only when: 1. a valid command had been recei ved(i.e. no framing error); 2. a state change did not occur during the spi message (if the b it is being returned as a 0 and a fault change occurs during th e middle of the spi message, the latch remains set). the latch is cleare d on the trailing (rising) edge of the cs pulse. note, to prevent missing any faults the clintx command should n ot generally clear any faults without being observed; i.e. it s hould only clear faults returned in the prior null response. table 8. command list command name description 000x xxxx null these commands are used to read ic status. these commands do no t change any internal ic status. returns status register 0-3, depending on sub command. 0010 xxxx mask0 sets a portion of the interrupt mask using lower four bits of c ommand. a 1 bit enables interrupt generation for this flag. int remains asserted if unc leared faults are still presen t. returns status register 0. 0011 xxxx mask1 sets a portion of the interrupt mask using lower four bits of c ommand. a 1 bit enables interrupt generation for this flag. int remains asserted if unc leared faults are still presen t. returns status register 0. 010x xxxx mode enables desat/phase error mode . enables fullon mode. locks furt her mode changes. returns status register 0. 0110 xxxx clint0 clears a portion of the fault latch corresponding to mask0 usin g lower four bits of command. a 1 bit clears the interrupt latch for this flag. int remains asserted if other unmasked fau lts are still present. returns status register 0. 0111 xxxx clint1 clears a portion of the fault latch corresponding to mask1 usin g lower four bits of command. a 1 bit clears the interrupt latch for this flag. int remains asserted if other unmasked fau lts are still present. returns status register 0. 100x xxxx deadtime set deadtime with calibration tec hnique. returns status registe r 0.
analog integrated circuit device data nxp semiconductors 35 33gd3000 7.2.3 null commands this command is sent by sending binary 000x xxxx data. this can be used to read ic status in the spi return word. message 000x xx00 reads status register 0. message 000x xx01 through 000x xx11 re ad additional internal registers. 7.2.3.1 mask command this is the mask for interrupts. a bit set to 1 enables the c orresponding interr upt. because of the nu mber of mask bits, thi s register is in two portions: 1. mask0 2. mask1 both are accessed with 0010 xxxx and 0011 xxxx patterns respect ively. figure 18 illustrates how interrupts are enabled and faults cleared. clint0 and clint1 ha ve the same format as mask0 and mask1 respe ctively, but the action is to cl ear the interrupt latch and sta tus register 0 bit corresponding to the lower nibble of the command . 7.2.3.2 interrupt handling figure 18. interrupt handling table 9. null commands spi data bits 7 6 5 4 3 2 1 0 write 000xxx00 reset null commands are described in d etail in the status registers s ection of this document. table 10. mask0 register spi data bits 7 6 5 4 3 2 1 0 write 0010xxxx reset 1111 table 11. mask1 register spi data bits 76543210 write 0011xxxx reset 1111 to status register various faults from clint command from maskx:n register fault net 0 net n int mask bit int clear int source s r latch
analog integrated circuit device data 36 nxp semiconductors 33gd3000 7.2.4 mode command this command is sent by s ending binary 010x xxxx data. table 12. setting interrupt masks mask:bit description mask0:0 overtemperature on any gate drive output generat es an interrupt if this bit is set. mask0:1 desaturation event on any output generates an interrupt if this bit is set. mask0:2 vls undervoltage generates an interrupt if this bit is set. mask0:3 overcurrent error Cif the overcurrent comparator threshold is exceeded, an interr upt is generated. mask1:0 phase error Cif any phase comparator output is not at the expected value wh en an output is command on, an interrupt is generated. this signal is the xor of the p hase comparator output with the output drive state, and blacked for the duration of the desatur ation blanking interval. in fullon mode, this signal is blanked and cannot generate an e rror. mask1:1 framing error Cif a framing error occurs, an interrupt is generated. mask1:2 write error after locking. mask1:3 reset event Cif the ic is reset or disabled, an interrupt occurs. since the ic always starts from a reset condition, this can be used to test the interrupt mechanism because when the ic comes out of r eset, an interrupt immediately occurs. table 13. mode command spi data bits 76543210 write 0100 desaturation fault mode 0 fullon mode mode lock reset 0000 ? bit 0 C mode lock is used to enable or disable m ode lock. this bit can only be c leared with a device rese t. since the mode lock mode can only be set, this bit prevents any subsequent, and lik ely erroneous, mode, deadtime, or mask register changes from be ing received. if an attempt is made to write to a regi ster when mod e lock is enabled, a write error fault is generated. ? bit 1 C fullon mode. if this bit is set, programmed deadtime control is disabled, m aking it is possible to have both high and low- side drivers in a phase on simul taneously. this could be useful in special applications such as alternator regulators, or swit ched- reluctance motor drive applications. there is no deadtime contr ol in fullon mode. input signals directly control the output st ages, synchronized with t he internal clock. this bit is a 0, a fter reset. until overwr itten, the ic opera tes normally; deadtime control and logic prevents both outputs from being turned on simultaneously. ? bit 3 C desaturation fault mode controls what happen when a des aturation event is detected. wh en set to 0, any desaturation on any channel causes all six output drivers to shutoff. the dr ivers can only be re-enabled by ex ecuting the clint command. wh en 1, desaturation faults a re completely ignored. bit 3 controls behavior if a desa turation, or phase error event is detected. the possibilities are: 0: default: when a desaturation , or phase error event is dete cted on any channel, all channel s turn off and generates an interrupt, if interrupts are enabled. 1: disable: desaturation /pha se error channel shutdown is dis abled, but interrupts are still possible if unmasked. sending a mode command and setti ng the mode lock simultaneously are allowed. this sets the requested mode and locks out any further changes.
analog integrated circuit device data nxp semiconductors 37 33gd3000 7.2.5 deadtime command deadtime prevents the turn-on of both transistors in the same p hase until the deadtime has expired. the deadtime timer starts when a fet is commanded off (see figure 6 and figure 13 ). the deadtime contro l is disabled by enabl ing the fullon mode . the deadtime is set by sending the deadtime command (100x xxx1) , and then sending a calibration pulse of cs . this pulse must be 16 times longer than the required deadtime (see figure 19 ). deadtime is measur ed in cycle times of t he internal time bas e, f tb . this measurement is divided by 16 and stored in an internal register to provide the reference for timing the deadtim e between high and low gate transactions i n the same phase. for example: the internal time base is running at 20 mhz and a 1.5 s deadtime is required. f irst a deadtime command is sent ( using the spi), then a cs is sent. the cs pulse is 16*1.5 = 24 s wide. the ic measures this pulse as 24 000 ns/50 ns = 480 clock cycles and stores 480/16 = 30 in the deadtim e register. until the next dea dtime calibration is performed, 30 clock cycles separate the tu rn off and turn on gate signals in the same phase. the worst case error immedia tely after calibrati on is +0/-1 ti me base cycle, fo r this examp le +0 ns/- 50 ns. note that if the internal time base drifts, the effect o n dead time scales directly. sending a zero deadtim e command (100x xxx0) sets the deadtime t imer to 0. however, simultaneou s turn-on of high-side and low- side fets in the same phase is still prevented unless the fullo n command has been transmitted. there is no calibration pulse e xpected after receiving the zero deadtime command. after reset, deadtime is set to the maximum value of 255 time b ase cycles (typically 15 s). the ic ignores any spi data which is sent during the calibratio n pulse. if there are any transitions on si or sclk while the d eadtime cs pulse is low, a frami ng error is generated , however, the cs pulse is used to cal ibrate the deadtime figure 19. deadtime calibration 7.2.6 status registers after any spi command, the status of the ic is reported in the return value from the spi port. t here are four variants of the null command used to read various status in th e ic. other commands return a general status word in the status register 0. there are four status registers in the ic. status register 0 is most commonly used for general status. registers one through t hree are used to read or confirm internal ic settings. 7.2.6.1 status register 0 (status latch bits) this register is read by sendin g the null0 command (000x xx00). it is also returned after any other command. this command retu rns the following data: table 14. .deadtime command spi data bits 7 6 5 4 3 2 1 0 write 100xxxx zero/ calibrate reset xxxx cs sclk si so deadtime command deadtime calibration pulse deadtime calibration pulse deadtime command cs sclk si so
analog integrated circuit device data 38 nxp semiconductors 33gd3000 7.2.6.2 status register 1 (mode bits) this register is read by sending the null1 command (000x xx01). this is guaranteed to not affec t ic operation and returns the following data: table 15. status register 0 spi data bits 76543210 results register 0 read reset event write error framing error phase error overcurrent low vls desat detected on any channel tlim detected on any channel reset 10000000 all status bits are latched. the latches are cleared only by se nding a clint0 or clint1 command with the appropriate bits set. if the status is still present, this b it does not clear. clint0 and clint1 have the same format as m ask0 and mask1 respectively. ? bit 0 Cis a flag for overtemperature on any channel. this bit is the or of the latched three intern al tlim detectors.this flag can generate an interrupt if the appropriate mask bit is set. ? bit 1 Cis a flag for desaturation detection on any channel. this bit is the or of the latched three intern al high-side desaturation detectors and phase error logic. f aults are also detected on th e low-side as phase errors . a phase error is generated if the output signal (at px_hs_s) does not properly reflect the drive conditi ons. the phase error is the triple or of phase errors from each phase. each phase error is the or of the hs and ls phase errors. an hs phase error (which also triggers the desaturation detector) oc curs when the hs fet is commanded on , and the px_hs_s is still low in the deadtime duration after it is driven on. similarly, a l s phase error occurs when the ls f et is commanded on, and the px_ hs_s is still high in the deadtime duratio n after the fet is driven on. this flag can genera te an interrupt if the appropria te mask bit is set. ? bit 2 C is a flag for low supply voltage . this flag can generate an inte rrupt if the appropriate mask b it is set. ? bit 3 Cis a flag for the output of the overcurrent comparator . this flag can generate an interrupt if the appropriate mask b it is set. ? bit 4 Cis a flag for a phase error . if any phase comparator output is not at the expected value w hen just one of the individual high or low-side outputs is enabled, t he fault flag is set. this sig nal is the xor of the phase comparator out put with the output d river state, and blanked for the duration of the desaturation blankin g interval. this flag can generat e an interrupt if the appropri ate mask bit is set. ? bit 5 Cis a flag for a framing error . a framing error is a spi messa ge not containing one or more m ultiples of eig ht bits. sclk toggling while measuring the dead time calibration pulse is also a framing error. this would typically be a transient or perman ent hardware error, perhaps due to noise on the spi lines. this fla g can generate an interrupt if the appropriate mask bit is set. ? bit 6 Cindicates a write error after the lock bit is set. a write error is a ny attempted writ e to the maskn, mode, or a deadtime command after the mode lock bit is set. a write error is any at tempt to write any other command than the one defined in the table 8 . this would typically be a softwa re error. this flag can generat e an interrupt if the appropriate mask bit is set. ? bit 7 Cis set upon exiting rst . it can be used to t est the interrupt mechanism or to flag for a condition where the ic gets reset without the host being otherwise aware. this flag can generate an interrupt if the appr opriate mask bit is set. table 16. status register 1 spi data bits 7 6 5 4 3 2 1 0 results register 1 read 0 desaturation mode zero deadtime set calibration overflow deadtime calibration 0 fullon mode lock bit reset 00000000 ? bit 0 C lock bit indicates the ic registers (d eadtime, maskn, clintn, and mode) are locked. any subseq uent write to these registers is ignored and se ts the write error flag. ? bit 1 C is the present status of fullon mode . if this bit is set to 0, t he fullon mode is not allowed. a 1 indicates the ic can operate in fullon mode (both high-side and low-side fets of one phase can be simultaneously turned on). ? bit 3 Cindicates deadtime calibration occurred. it is 0 until a successful deadtime command is exe cuted. this includes the zero deadtime setting, as well as a calibration overflow. ? bit 4 Cis a flag for a deadtime calibration overflow . ? bit 5 Cis set if zero deadtime is commanded. ? bit 6 Creflects the current state of the desaturation/phase error turn-off mode.
analog integrated circuit device data nxp semiconductors 39 33gd3000 7.2.6.3 status register 2 (mask bits) this register is read by sending the null2 command (000x xx10). this is guaranteed to not affe ct ic operation and returns the following data: 7.2.6.4 status register 3 (deadtime) this register is read by sending the null3 command (000x xx11). this is guaranteed to not affe ct ic operation and returns the following data: 7.3 initialization requirements the 33gd3000 provides safe, de pendable gate control for 3 phase bldc motor control units when it is properly configured. howev er, if improperly initialized, the hi gh-side gate drive can be left in a high-impedance mode which allo ws charge to accumulate from e xternal sources, eventually turning on t he high-side output transistor. it is prudent to follow a well defined initialization procedur e which establishes known states on the gates of all the phase drivers before any c urrent flows in the motor. 7.3.1 recovery from sleep mode (reset) the output gate drive is pulled low with the hold off circuit a s long as vls is low, there is a power on reset condition or +5 .0 v is low. these conditions are present dur ing a reset condition. when fir st coming out of a reset condition, the gate drive circuits are in a high- impedance state until the first command is given for operation. after the reset line goes hig h, the supplies begin to operate and the hold off circuit is deactivated. the phase input lines do not have a ny effect on the gate drive unti l both enable1 and enable2 go h igh and even then, the low-side gate must be commanded on before the hi gh-side gate can be operated. this is to ensure the bootstrap c apacitor has been charged befor e commencing normal operation. then the h igh-side gate must be commanded o n and then off to initialize t he output latches. a proper initia lization sequence places the out put gate drives in a low-impedanc e known condition prior to rel easing the device for normal operation. a valid initialization sequence would go something like this: 1. reset goes high (enable1 and enable2 remain low) 2. spi commands to configure vali d interrupts, desat mode and de ad time are issued 3. spi command to clear all interrupt conditions 4. enable1 and enable2 are set hig h (ls outputs are now enabled) 5. pa_ls, pb_ls and pc_ls are t oggled high for about 1us (hs out puts are enabled, but not latched) 6. toggle npa_hs, npb_hs and npc_hs low for dead time plus at le ast 0.1 s (hs outputs are now latched and operational). end of initialization. doing step 6 simultaneously on a ll hs inputs places the motor i nto high-side recirculation mode and does not cause motion duri ng the time they are on. this action forc es the high-side gate drive o ut of tri-state mode and leave it with the hs_g shorted to hs_s on all phases. the hs output fets is off and ready for normal motor co ntrol. step 5 and step 6 can be done on all the stated inputs simultan eously. it may be desirable for the hs (step 6) to be toggled s imultaneously to prevent current from flowing in the motor dur ing initializat ion. table 17. status register 2 spi data bits 7 6 5 4 3 2 1 0 results register 2 read mask1:3 mask1:2 mask1:1 mask1:0 mask0:3 mask0:2 mask0:1 mask0:0 reset 11111111 table 18. status register 3 spi data bits 7 6 5 4 3 2 1 0 results register 3 read dead7 dead6 dead5 dead4 dead3 dead2 dead1 dead0 reset 00000000 these bits represent the calibra tion applied to the internal os cillator to generate the requested deadtime. if calibration is not yet performed, all these bits return 0 even though t he actual dead time is th e maximum.
analog integrated circuit device data 40 nxp semiconductors 33gd3000 note the inputs pa_ls, pb_ls, pc _ls, npa_hs, npb_hs and npc_hs are edge sensitive. toggling the ls inputs enables the hs drivers, so for the hs drivers to be initialized correctly the edge of the input signal to the hs drivers must come after the ls input toggle. a failure to do this results in the hs gate output remaining in a high-impedance mode. this can result in an accumulation of c harge, from internal and external leakage sources, on the gate of the hs ou tput fet causing it to turn on even though the input level to t he 33gd3000 would appear to indicate it should be off. when this happens, the logic of the 33gd3000 allows the ls outp ut fet to be turned on without t aking any action on the hs gate because the logic is still indicating t he hs gate is off. the initial l s input transition from low to high needs to be a fter both enab le inputs are high (the device in normal mode) for the same reason. the delay between enable and the ls input should be 280 ns minimum to en sure the device is out of stby mode. once initialized the output gat e drives continues to operate i n a low-impedance mode as comman ded by the inputs until t he next reset event. figure 20. full initialization table 19. full initialization timing description time description min. comments t pu_vdd , t pu_vls power up time from reset 2.0 ms reset must remain high long enough for vdd and vls to reach the full regulated voltage. the normal time for this to occur is s pecified as 2.0 ms maximum. i f there is more capacitance on vls or vdd than the normal values given in the specification, t his time may need to be increased. in general, the time may be safely scaled linearly w ith the capacitance. if the charge pump is used it may also increas e this time. an estimate of inc reased time, due to the charge pump, would be to add 25%. for example, the nominal vls capacit ance is 2.2 f on each pin, the power up time should be increas ed to 4.0 ms, 5.0 ms if usin g the charge pump. t 1 end of spi communication to en1 and en2 rising edge 0 ns t 2 en1 and en2 rising edge to first ls output command 280 ns restricted by en1 and en2 propagation delay t 3 initial ls on period 1.0 s nominally 1.0 s is more than enough. the calculated value is 5 *c boot (r sense + r dson_ls ). 100 ns for default recovery. int spi cs px_hs px_ls en1-2 rst vdd vls vpwr vsup t pu_vdd t pu_vls t 1 t 2 t 4 t 5 t 6 t 3
analog integrated circuit device data nxp semiconductors 41 33gd3000 7.3.2 recovery from sta ndby mode or a fault when the 33gd3000 is placed in standby mode or a fault conditio n causes a shutdown, the gate out puts are all driven low. the h igh-side gate drive is then di sabled and locked to prevent unauthorized transitions. this requires an initialization sequence to recove r normal operation at the en d of this mode of opera tion. the initializat ion sequence is nearly identical to recovery from sleep mode, w ith the modification that the initial pulse to the low-side control inp uts can be reduced to a 100 ns pulse (the l ow-side gates may no t actually change state). then the initialization is completed by cycling the high-side gates to re-engage the gate drive and ensure it i s in the proper state prior to resum ing normal operation. a valid initialization sequence would go something like this: 1. spi command to clear all interrupt conditions 2. enable1 and enable2 are set hig h (ls outputs are now enabled) 3. pa_ls, pb_ls and pc_ls are toggled high for at least 100 ns ( hs gate drive outputs are enabl ed) longer if bootstrap capacito rs need charged. 4. toggle npa_hs, npb_hs and npc_hs low for dead time plus at le ast 100 ns. end of initialization. doing step 4 simultaneously on al l hs inputs, places the motor into high-side recirculation mode and does not cause motion dur ing the time they are on. this action restores the high-si de gate drive operation and lea ve it with the hs_g shorted to hs_s on all phases. the hs outpu t fets is off and ready for normal motor control. step 3 and step 4 can be done on all the stated inputs simultan eously. in fact it is desirable for the hs (step 4) to be toggl ed simultaneously to prevent current from flowing in the motor dur ing initializat ion. note the inputs pa_ls, pb_ls, pc _ls, npa_hs, npb_hs and npc_hs are edge sensitive. toggling the ls inputs enables the hs drivers, so for the hs drivers to be initialized correctly the edge of the input signal to the hs drivers must come after the ls input toggle. a failure to do this results in the hs gate outpu t remaining lo cked out from input control. the initial ls input transition fr om low to high needs to be after both enable i nputs are high (the device in no rmal mode) for the same reason. the delay between enable and th e ls input should be 280 ns minimum to ensure the device is out o f stby mode. figure 21. recovery initialization the horizontal divisions are not to scale, they are a reference to show the sequence of operation. either individual npx_hs an d px_ls or npx_combined may be used. npx_co mbined is defined as both npx_h s and px_ls tied together or oper ated to the same logic level simultaneously. t 4 ls of to hs on 0 ns no defined maximum, but hs is undefined until beginning of toggle on the hs t 5 initial hs on period 100 ns + dead time minimum: dead-time + 100 ns to guarantee the hs is switched. maximum: same limitations as normal operation. unlimited time i f leakage currents are less than trickle charge pump margin. t 6 hs off to normal operation 0 ns immediately begin normal operatio n table 19. full initialization timing description time description min. comments int spi ncs px_combined npx_hs px_ls en2 en1 clear 0.1 s 0.1 s
analog integrated circuit device data 42 nxp semiconductors 33gd3000 7.3.3 ic initialization this process flow initializes t he ic and its sof tware environme nt. 1. apply power (v sys ) to module 2. remove rst (rst goes high, en1 and en2 are still low) 2.1. when rst rises above the threshold, the d evice powers up. the charge pu mp (if configured) starts, allow v dd and v ls to stabilize. 3. initialize registers 3.1. clear all interrupt statu s flags (send ci nt0 and cint1) 3.2. initialize mask register by sendin g 0010 xxxx or 0011 xxxx to mask out unwanted interrupts. 3.3. set desired dead time either by commanding zero dead time or calibrating the dead time. 3.4. send mode comm and with desired bits, and also the lock bit . e.g. 01000001. this prev ents further mode changes. 4. bring en1 and en2 high 5. initialize the outputs 5.1. command all px_hs to logic 1 (high-side off) 5.2. command all px_ls to logic 1 (commanding low-side on). the input must transition from low to high after en1 and en2 have gone high. 5.3. wait for the bootstrap capac itors to charge (about 1 us ty pically) 5.4. command all px_ls to logic 0 (command low-side off) 5.5. command all px_hs to logic 0 (command high-side on) 5.6. command all px_hs to logic 1 (command high-side off) the device is now ready for normal operation. 7.3.4 interrupt handler when an interrupt occurs, the general procedure is to send null 0 and null1 commands to determine what happened, take correctiv e action (if needed), clear the faul t and return. because the ret urn value from an sp i command is actually r eturned in the subse quent message, main-loop software tries to read sr1, sr2, or sr3, may experience an interrupt between sending the spi command and th e subsequent read. thus if these reg isters are to be read, specia l care must be taken in the software to ensure the correct resu lts are being interpreted.
analog integrated circuit device data nxp semiconductors 43 33gd3000 8 typical applications figure 22. typical application d iagram using charge pump (+12 v battery system) vsup vpwr pump vpump pgnd main charge pump oscillator uv detect 5v reg. vdd control logic t-lim rst en1 en2 int px_hs px_ls 3 3 cs si sclk so phase_x 3 oc_out oc_th amp_out amp_n amp_p vls_cap px_ls_s px_ls_g px_hs_g px_hs_s px_boot vdd vls trickle charge pump hold -off circuit high -side driver low -side driver vls reg. i-sense amp. over-cur. comp. phase comp. desat. comp. to motor 3 x + - + - v sys + - vsup vsup 1.4v gnd to other two phases +12v nom. phase x output to adc r g_hs r g_ls (optional) (optional) c x_boot r sense phase return vpwr pump d1 d2 c1 c2 c6 c3 c5 c4 r1 r2 r3 r fb q hs q ls
analog integrated circuit device data 44 nxp semiconductors 33gd3000 figure 23. power dissipation profile of application using char ge pump reference application with: ? pump capacitor: 1.0 f mlc ? pump filter capacitor: 47 f low esr aluminum electrolytic ? pump diodes: mur120 ? output fet gate charge: 240 nc @ 10 v ? pwm frequency: 20 khz ? switching single phase below approximately 17 v the char ge pump is actively regulating v pwr . the increased power dissipatio n is due to the charge pump losses. above this voltage the c harge pump oscillator shuts dow n and v sys is passed through the pu mp diodes directly to v pwr . 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 5 10152025303540 supply voltage (v) power dissipated (w)
analog integrated circuit device data nxp semiconductors 45 33gd3000 figure 24. power dissipation profile of application not using charge pump reference application with: ? output fet gate charge: 240 nc @ 10 v ? pwm frequency: 20 khz ? switching single phase ? no connections to pump or vpump ? vpwr connected to v sys if vpwr is supplied by a separate pre-regulator, the power diss ipation profile is nearly flat at the value of the pre-regulato r voltage for all v sys voltages. 0.000 0.100 0.200 0.300 0.400 0.500 0.600 0.700 0.800 0.900 1.000 1.100 1.200 1.300 1.400 1.500 10 15 20 25 30 35 40 45 50 55 60 supply voltage (v) power dissipation (w)
analog integrated circuit device data 46 nxp semiconductors 33gd3000 9 packaging 9.1 package mechanical dimensions package dimensions are provided in package drawings. to find th e most current package outline drawing, go to www.nxp.com and perform a keyword search for t he drawings document number. . table 20. packaging information package suffix package outline drawing number 56-pin qfn ep 98asa00654d
analog integrated circuit device data nxp semiconductors 47 33gd3000
analog integrated circuit device data 48 nxp semiconductors 33gd3000
analog integrated circuit device data nxp semiconductors 49 33gd3000 10 revision history revision date description of changes 1.0 4/2015 ? initial release 2.0 5/2015 ? updated thermal resistance value and unit in table 3 7/2015 ? changed part number from pc to mc in the orderable parts on page 2 8/2015 ? corrected operating junction temperature value in table 3 3.0 10/2015 ? revised v esd values in table 3 4.0 12/2015 ? corrected upper end operating range value on page 1 ? corrected v sup value in table 3 5.0 6/2018 ? updated targeted application on page 1 6.0 8/2018 ? added aec-q100 grade 1 qualified to general description and features list on page 1
document number: mc33gd3000 rev. 6.0 8/2018 information in this document is provided solely to enable syste m and software implementers to use nxp products. there are no expressed or implied copy right licenses granted hereunde r to design or fabricate any integrated circuits based on the information in this document. nxp reserves the right to mak e changes without further not ice to anyproducts herein. nxp makes no warranty, representation, or guarantee regarding t he suitability of its products for any particular purpose, nor does nxp assume any liability arising out of the applicatio n or use of any product or circui t, and specifically disclaims any and all liability, including without limitation, consequent ial or incidental damages. "typical" parameters that may be provided in nxp data sheets and/or specifications can and do va ry in different applications, and actual performance may vary over time. all operating parameters, including "typicals," must be validated for each customer application by the customer's technical experts. nx p does not convey any license u nder its patent rights nor the rights of others. nxp sells products pursuant to standard terms and conditions of sale, whi ch can be found at the following address: http://www.nxp.com/terms-of-use.html . nxp, the nxp logo, freescale, the freescale logo and smartmos a re trademarks of nxp semiconductors b.v. all other product or service names are the property of their re spective owners. all rights reserved. ? nxp b.v. 2018. how to reach us: home page: nxp.com web support: http://www.nxp.com/support

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